Memory cells in a nonvolatile memory (NVM) device may malfunction due to various impairments. Some memory devices keep track of and avoid using non-functional memory cells. Methods for managing failing memory cells are known in the art. For example, U.S. Pat. No. 9,058,261, whose disclosure is incorporated herein by reference, describes embodiments that are directed to providing detailed error reporting of data operations performed on a NVM storage device. In one embodiment, a controller interfaces with a NVM storage device including NVM storage coupled with a bridge. In one embodiment, the controller is provided physical, page-level access to the NVM via the bridge, and the bridge provides detailed error reporting of the data operations that the bridge performs on the NVM on behalf of the controller. For example, the bridge may provide page level reporting indicating which page(s) failed during a read operation. Detailed error reporting allows the controller to better understand the failures that occurred in a data access operation in the NVM.
U.S. Pat. No. 9,305,663, whose disclosure is incorporated herein by reference, describes examples of assessing pass/fail status of a non-volatile memory. In some examples, information may be received to indicate a block having memory pages associated with non-volatile memory cells. The information may indicate at least some of the memory pages have bit errors in excess of an error correction code (ECC) ability to correct. For these examples, the block may be selected for read testing. Read testing may include programming the memory pages with a known pattern and waiting a period of time. Following the period of time each memory page may be read and if a resulting pattern read matches the known pattern programmed to each memory page, the memory page passes. The block may be taken offline if the number of passing memory pages is below a pass threshold number.